第一篇：多功能數(shù)字鐘課程設(shè)計VHDL代碼書上程序改
library ieee;use ieee.std_logic_1164.all;entity clock is port(clk1hz:in std_logic;--1hz脈沖--clk100:in std_logic;--100hz脈沖--weekclk:in std_logic;--星期調(diào)整脈沖--start_stop:in std_logic;--秒表啟動/停止控制--reset:in std_logic;--秒表復(fù)位--adclk:in std_logic;--校時脈沖--setselect:in std_logic;--調(diào)整位選擇脈沖--mode:in std_logic;--功能選擇脈沖--showdate:in std_logic;--日期顯示--dis:out std_logic_vector(23 downto 0);--顯示輸出--glisten:out std_logic_vector(5 downto 0);--閃爍指示--weekout:out std_logic_vector(3 downto 0);--星期輸出--qh:out std_logic--整點報時--);end clock;architecture arch of clock is component adjust
port（adclk: in std_logic;
data_in: out std_logic_vector(7 downto 0));end component;component control
port（setclk: in std_logic;
setlap: out std_logic_vector(1 downto 0);
mode: in std_logic;
module: out std_logic_vector(2 downto 0));end component;component weekcounter
port（clk: in std_logic;
clk2: in std_logic;
q: out std_logic_vector(3 downto 0));end component;component stopwatch
port（clk: in std_logic;
reset: in std_logic;
start_stop: in std_logic;
centsec: out std_logic_vector(7 downto 0);
sec: out std_logic_vector(7 downto 0);
min: out std_logic_vector(7 downto 0));end component;component h_m_s_count
port（clk: in std_logic;
set: in std_logic;
setlap: in std_logic_vector(1 downto 0);
d:in std_logic_vector(7 downto 0);
sec:out std_logic_vector(7 downto 0);
min:out std_logic_vector(7 downto 0);
hour:out std_logic_vector(7 downto 0);
qh:out std_logic;
qc: out std_logic);end component;component y_m_d_count
port（clk: in std_logic;
set: in std_logic;
setlap: in std_logic_vector(1 downto 0);
data_in: in std_logic_vector(7 downto 0);
day: out std_logic_vector(7 downto 0);
month: out std_logic_vector(7 downto 0);
year: out std_logic_vector(7 downto 0));end component;component display
port（module: in std_logic_vector(2 downto 0);
showdate:in std_logic;
clk:in std_logic;
setlap:in std_logic_vector(1 downto 0);
watch: in std_logic_vector(23 downto 0);
time:in std_logic_vector(23 downto 0);
date:in std_logic_vector(23 downto 0);
dis: out std_logic_vector(23 downto 0);
glisten:out std_logic_vector(5 downto 0));end component;signal data_in,mcentsec,msec,mmin,ssec,smin,shour,sdate,smonth,syear:std_logic_vector(7 downto 0);signal setlap:std_logic_vector(1 downto 0);signal module:std_logic_vector(2 downto 0);signal qc:std_logic;signal watch,time,date:std_logic_vector(23 downto 0);begin u1:adjust port map(adclk,data_in);u2:control port map(setselect,setlap,mode,module);u3:stopwatch port map(clk100,reset,start_stop,mcentsec,msec,mmin);u4:h_m_s_count port map(clk1hz,module(1),setlap,data_in,ssec,smin,shour,qh,qc);u5:y_m_d_count port map(qc,module(2),setlap,data_in,sdate,smonth,syear);u6:display port map(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten);u7:weekcounter port map(qc,weekclk,weekout);watch<=mmin&msec&mcentsec;time<=shour&smin&ssec;date<=syear&smonth&sdate;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adjust is
port（adclk: in std_logic;
data_in: out std_logic_vector(7 downto 0));end adjust;architecture arch of adjust is signal temp2,temp1:std_logic_vector(3 downto 0);begin process(adclk)begin if rising_edge(adclk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;data_in<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control is
port（setclk: in std_logic;--調(diào)整脈沖--
setlap: out std_logic_vector(1 downto 0);--調(diào)整位選擇脈沖--
mode: in std_logic;--功能選擇脈沖--
module: out std_logic_vector(2 downto 0)--功能輸出--);end control;architecture arch of control is signal ssetlap:std_logic_vector(1 downto 0);signal s:std_logic_vector(3 downto 0);begin process(mode,setclk)begin if mode='1'then ssetlap<=“00”;elsif rising_edge(setclk)then if ssetlap=“10”then ssetlap<=“00”;else ssetlap<=ssetlap+'1';end if;end if;end process;setlap<=ssetlap;process(mode)begin if rising_edge(mode)then case s is when“0001”=>s<=“0010”;when“0010”=>s<=“0100”;when“0100”=>s<=“1000”;when“1000”=>s<=“0001”;when others=>s<=“0010”;end case;end if;end process;module<=s(3 downto 1);end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter60 is
port（clk: in std_logic;--計數(shù)脈沖--
clr: in std_logic;--復(fù)位--
q: out std_logic_vector(7 downto 0);--計數(shù)值--
qc:out std_logic--進位輸出--);end counter60;architecture arch of counter60 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter99 is
port（clk: in std_logic;--100vhz計數(shù)脈沖--
en: in std_logic;--計數(shù)使能--
clr: in std_logic;--復(fù)位--
q: out std_logic_vector(7 downto 0);--計數(shù)值--
qc: out std_logic--進位--);end counter99;
architecture arch of counter99 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if en='1' then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity daycounter is
port（clk: in std_logic;--計數(shù)脈沖--
set: in std_logic;--調(diào)整信號--
day_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--
day_out: out std_logic_vector(7 downto 0);--天輸出--
qc: out std_logic;--進位--
day28: in std_logic;--該位為1表示該月為28天--
day29: in std_logic;--該位為1表示該月為29天--
day30: in std_logic;--該位為1表示該月為30天--
day31: in std_logic--該位為1表示該月為31天--);end daycounter;architecture arch of daycounter is signal temp1,temp2:std_logic_vector(3 downto 0);signal days:std_logic_vector(7 downto 0);begin days<=“00101000” when day28='1'else
“00101001”when day29='1'else
“00110000”when day30='1'else
“00110001”when day31='1'else
“00000000”;process(clk,set,day_in,days)begin if set='1' then temp2<=day_in(7 downto 4);temp1<=day_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2&temp1=days then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;day_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity days_control is port（month: in std_logic_vector(7 downto 0);--月份--
year2: in std_logic;--年份高位數(shù)字bcd碼最低位--
year1: in std_logic_vector(1 downto 0);--年份低位數(shù)字bcd碼末兩位--
day28: out std_logic;--該位為1表示該月為28天--day29: out std_logic;--該位為1表示該月為29天--
day30: out std_logic;--該位為1表示該月為30天--
day31: out std_logic--該位為1表示該月為31天--);end days_control;architecture arch of days_control is begin process(month,year2,year1)begin case month is when “00000001”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000010”=>if(year2='0'and year1=“00”)or(year2='1'and year1=“10”)then
day28<='0';day29<='1';day30<='0';day31<='0';
else
day28<='1';day29<='0';day30<='0';day31<='0';
end if;when “00000011”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000100”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000101”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000110”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000111”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00010001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010010”=>day28<='0';day29<='0';day30<='0';day31<='1';when others=>day28<='0';day29<='0';day30<='0';day31<='1';end case;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity display is
port（module: in std_logic_vector(2 downto 0);--功能選擇--
showdate:in std_logic;--顯示日期--
clk:in std_logic;--閃爍脈沖--
setlap:in std_logic_vector(1 downto 0);--閃爍位選擇--
watch: in std_logic_vector(23 downto 0);--秒表計數(shù)值輸入--
time:in std_logic_vector(23 downto 0);--時分秒計數(shù)值輸入--date:in std_logic_vector(23 downto 0);--年月日計數(shù)值輸入--
dis: out std_logic_vector(23 downto 0);--顯示輸出--
glisten:out std_logic_vector(5 downto 0)--閃爍輸出--);end display;architecture arch of display is begin process(module,showdate,watch,time,date)begin if showdate='1'then dis<=date;else case module is when“001”=>dis<=watch;when“010”=>dis<=time;when“100”=>dis<=date;when others=>dis<=time;end case;end if;end process;process(clk,module,setlap)begin if module=“010”or module=“100”then case setlap is when“00”=>glisten(1 downto 0)<=clk&clk;
glisten(5 downto 2)<=“0000”;when“01”=>glisten(3 downto 2)<=clk&clk;
glisten(5 downto 4)<=“00”;
glisten(1 downto 0)<=“00”;when“10”=>glisten(5 downto 4)<=clk&clk;
glisten(3 downto 0)<=“0000”;when others=>glisten<=“000000”;end case;else glisten<=“000000”;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity dmux is
port（set:in std_logic;--調(diào)整信號--
setlap: in std_logic_vector(1 downto 0);--調(diào)整位選擇--
d: in std_logic_vector(7 downto 0);--調(diào)整輸入--
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end dmux;architecture arch of dmux is begin process(set,setlap,d)begin if set='1' then case setlap is when“00”=>set1<='1';set2<='0';set3<='0';
q1<=d;when“01”=>set1<='0';set2<='1';set3<='0';
q2<=d;when“10”=>set1<='0';set2<='0';set3<='1';
q3<=d;when others=>set1<='0';set2<='0';set3<='0';end case;else set1<='0';set2<='0';set3<='0';end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity h_m_s_count is
port（clk: in std_logic;--1hz脈沖--
set: in std_logic;--調(diào)整信號--
setlap: in std_logic_vector(1 downto 0);--調(diào)整位選擇--
d:in std_logic_vector(7 downto 0);--調(diào)整輸入--
sec:out std_logic_vector(7 downto 0);--秒輸出--
min:out std_logic_vector(7 downto 0);--分輸出--
hour:out std_logic_vector(7 downto 0);--小時輸出--
qh:out std_logic;--整點報時--
qc: out std_logic--進位--);end h_m_s_count;architecture arch of h_m_s_count is component sec_mincounter
port（clk: in std_logic;
set:in std_logic;
d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(7 downto 0);
qc:out std_logic);end component;component hourcounter port（clk: in std_logic;
set:in std_logic;
d:in std_logic_vector(7 downto 0);
q: out std_logic_vector(7 downto 0);
qc:out std_logic);end component;component dmux
port（set:in std_logic;
setlap: in std_logic_vector(1 downto 0);
d: in std_logic_vector(7 downto 0);
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end component;signal secset,minset,hourset: std_logic;signal secin,minin,hourin:std_logic_vector(7 downto 0);signal qcsec,qcmin,qchour: std_logic;begin u1:dmux port map(set,setlap,d,secset,minset,hourset,secin,minin,hourin);u2:sec_mincounter port map(clk,secset,secin,sec,qcsec);u3:sec_mincounter port map(qcsec,minset,minin,min,qcmin);u4:hourcounter port map(qcmin,hourset,hourin,hour,qchour);qh<=qcmin;qc<=qchour;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity hourcounter is
port（clk: in std_logic;--計數(shù)脈沖--
set:in std_logic;--調(diào)整信號--
d:in std_logic_vector(7 downto 0);--調(diào)整時間--
q: out std_logic_vector(7 downto 0);--小時輸出--
qc:out std_logic--進位--);end hourcounter;architecture arch of hourcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0010” and temp1=“0100” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity monthcounter is
port（clk: in std_logic;--計數(shù)脈沖--
set: in std_logic;--調(diào)整信號--
month_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--
month_out: out std_logic_vector(7 downto 0);--月輸出--
qc: out std_logic--進位--);end monthcounter;architecture arch of monthcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,month_in)begin if set='1' then temp2<=month_in(7 downto 4);temp1<=month_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0001”and temp1=“0010” then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;month_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sec_mincounter is port（clk: in std_logic;--計數(shù)脈沖--
set:in std_logic;--調(diào)整信號--
d:in std_logic_vector(7 downto 0);--調(diào)整時間輸入--
q:out std_logic_vector(7 downto 0);--分和秒輸出--
qc:out std_logic--進位--);end sec_mincounter;architecture arch of sec_mincounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity stopwatch is port（clk: in std_logic;--100hz脈沖--
reset: in std_logic;--復(fù)位--
start_stop: in std_logic;--啟動/停止--
centsec: out std_logic_vector(7 downto 0);--百分秒輸出，當(dāng)超過60分轉(zhuǎn)為秒--
sec: out std_logic_vector(7 downto 0);--秒輸出，當(dāng)超過60分轉(zhuǎn)為分--
min: out std_logic_vector(7 downto 0)--分輸出，當(dāng)超過60分轉(zhuǎn)為小時--);end stopwatch;architecture arch of stopwatch is component counter99 port（clk: in std_logic;
en: in std_logic;
clr: in std_logic;
q: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;component counter60 port（clk: in std_logic;
clr: in std_logic;
q: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;signal qc1,qc2,qc3,qc4,flag:std_logic;signal tcentsec,tsec,tmin,thour:std_logic_vector(7 downto 0);begin u1:counter99 port map(clk,start_stop,reset,tcentsec,qc1);u2:counter60 port map(qc1,reset,tsec,qc2);u3:counter60 port map(qc2,reset,tmin,qc3);u4:counter60 port map(qc3,reset,thour,qc4);process(qc3)begin if rising_edge(qc3)then flag<='1';end if;if flag='1' then centsec<=tsec;sec<=tmin;min<=thour;else centsec<=tcentsec;sec<=tsec;min<=tmin;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity weekcounter is
port（clk: in std_logic;--天脈沖--
clk2: in std_logic;--外部星期調(diào)整脈沖--
q: out std_logic_vector(3 downto 0)--星期輸出--);end weekcounter;architecture arch of weekcounter is signal temp:std_logic_vector(3 downto 0);signal cp:std_logic;begin cp<=clk or clk2;process begin wait until rising_edge(cp);if temp=“0111” then temp<=“0001”;else
temp<=temp+'1';end if;q<=temp;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity y_m_d_count is
port（clk: in std_logic;--計數(shù)脈沖--
set: in std_logic;--調(diào)整信號--
setlap: in std_logic_vector(1 downto 0);--調(diào)整位選擇--
data_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--
day: out std_logic_vector(7 downto 0);--日輸出--
month: out std_logic_vector(7 downto 0);--月輸出--
year: out std_logic_vector(7 downto 0)--年輸出--);end y_m_d_count;architecture arch of y_m_d_count is component daycounter
port（clk: in std_logic;
set: in std_logic;
day_in: in std_logic_vector(7 downto 0);
day_out: out std_logic_vector(7 downto 0);
qc: out std_logic;
day28: in std_logic;
day29: in std_logic;
day30: in std_logic;
day31: in std_logic);end component;component monthcounter
port（clk: in std_logic;
set: in std_logic;
month_in: in std_logic_vector(7 downto 0);
month_out: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;component yearcounter
port（clk: in std_logic;
set: in std_logic;
year_in: in std_logic_vector(7 downto 0);
year_out: out std_logic_vector(7 downto 0));end component;component dmux
port（set:in std_logic;
setlap: in std_logic_vector(1 downto 0);
d: in std_logic_vector(7 downto 0);
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end component;component days_control
port（month: in std_logic_vector(7 downto 0);
year2: in std_logic;
year1: in std_logic_vector(1 downto 0);
day28: out std_logic;
day29: out std_logic;
day30: out std_logic;
day31: out std_logic);end component;signal dayset,monthset,yearset: std_logic;signal qcday,qcmonth: std_logic;signal dayin,monthin,yearin: std_logic_vector(7 downto 0);signal smonth,syear:std_logic_vector(7 downto 0);signal day28,day29,day30,day31:std_logic;begin u1:dmux port map(set,setlap,data_in,dayset,monthset,yearset,dayin,monthin,yearin);u2:daycounter port map(clk,dayset,dayin,day,qcday,day28,day29,day30,day31);u3:monthcounter port map(qcday,monthset,monthin,smonth,qcmonth);u4:yearcounter port map(qcmonth,yearset,yearin,syear);u8:days_control port map(smonth,syear(4),syear(1 downto 0),day28,day29,day30,day31);month<=smonth;year<=syear;
end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yearcounter is
port（clk: in std_logic;--計數(shù)脈沖--
set: in std_logic;--調(diào)整信號--
year_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--
year_out: out std_logic_vector(7 downto 0)--年輸出--);end yearcounter;architecture arch of yearcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,year_in)begin if set='1' then temp2<=year_in(7 downto 4);temp1<=year_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;end process;year_out<=temp2&temp1;end arch;
第二篇：用狀態(tài)機實現(xiàn)的EDA多功能數(shù)字鐘課程設(shè)計VHDL代碼
設(shè)計并實現(xiàn)具有一定功能的數(shù)字鐘
1、該數(shù)字鐘可以實現(xiàn)3個功能：計時功能、整點報時功能和重置時間功能，因此有3個功能：計時、重置時間、復(fù)位。
2、對所有設(shè)計的小系統(tǒng)能夠正確分析；
3、基于VHDL語言描述系統(tǒng)的功能；
4、在quartus 2環(huán)境中編譯通過；
5、仿真通過并得到正確的波形；
6、給出相應(yīng)的設(shè)計報告。
其中計時模塊有4部分構(gòu)成：秒計時器（second）、分計時器(minute)、時計時器(hour)、日計時器(date)、月計時器（mouth）、年計時器（year）
1）秒計時器（second）是由一個60進制的計數(shù)器構(gòu)成的，具有清0、置數(shù)和計數(shù)功能。其中reset為清0信號，當(dāng)reset為0時，秒計時器清0；set 為置數(shù)信號，當(dāng)set為0時，秒計時器置數(shù)，置s1的值。clk為驅(qū)動秒計時器的時鐘，sec為秒計時器的輸出，ensec為秒計時器的進位信號，作為下一級的時鐘輸入信號。
2）分計時器（minute）是由一個60進制的計數(shù)器構(gòu)成的，具有清0、置數(shù)和計數(shù)功能。其中reset為清0信號，當(dāng)reset為0時，分計時器清0；set 為置數(shù)信號，當(dāng)set為0時，分計時器置數(shù)，置m1的值。clkm為驅(qū)動分計時器工作的時鐘，與ensec相連接；min為分計時器的輸出；enmin為分計時器的進位信號，作為下一級的時鐘輸入信號。
3）時計時器（hour）是由一個24進制的計數(shù)器構(gòu)成的，具有清0、置數(shù)和計數(shù)功能。其中reset為清0信號，當(dāng)reset為0時，時計時器清0；set 為置數(shù)信號，當(dāng)set為0時，時計時器置數(shù)，置h1的值。clkh為驅(qū)動時計時器工作的時鐘，與enmin相連接；hour為時計時器的輸出；enhour為時計時器的進位信號，作為下一級的時鐘輸入信號。
4）日計時器（date1）是由一個60進制的計數(shù)器構(gòu)成的，具有清0、置數(shù)和計數(shù)功能。其中reset為清0信號，當(dāng)reset為0時，星期計時器清0；set 為置數(shù)信號，當(dāng)set為0時，星期計時器置數(shù)，置d1的值。clkd為驅(qū)動星期計時器工作的時鐘，與enhour相連接；date為日計時器的輸出，endate為分計時器的進位信號，作為下一級的時鐘輸入信號，由于月份的天數(shù)存在天數(shù)不同，閏年2月的天數(shù)為28天等情況，還設(shè)計了一個潤年判別器，準(zhǔn)確顯示時間。
5）月計時器（mouth）是由一個60進制的計數(shù)器構(gòu)成的，具有清0、置數(shù)和計數(shù)功能。其中reset為清0信號，當(dāng)reset為0時，星期計時器清0；set 為置數(shù)信號，當(dāng)set為0時，星期計時器置數(shù)，置mou1的值，clkmou為驅(qū)動星期計時器工作的時鐘，與enday相連接；mou為日計時器的輸出，enmou為分計時器的進位信號，作為下一級的時鐘輸入信號。6）計時器（year）是由一個60進制的計數(shù)器構(gòu)成的，具有清0、置數(shù)和計數(shù)功能。其中reset為清0信號，當(dāng)reset為0時，星期計時器清0；set 為置數(shù)信號，當(dāng)set為0時，星期計時器置數(shù)，置y1的值，clky為驅(qū)動星期計時器工作的時鐘，與enmou相連接；year為日計時器的輸出。VHDL程序
1、屏幕切換模塊
運用狀態(tài)機進行屏幕切換，分別顯示年月日，以及時分秒 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux3 is
Port(clk,Reset,sel : in std_logic;
int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--rst must
a1,a2,a3,a4,a5,a6: out std_logic_vector(3 downto 0));end mux3;
architecture Behavioral of mux3 is
TYPE states IS(st0, st1, st2, st3, st4, st5, st6, st7);
SIGNAL STX: states;
begin
COM1 : PROCESS(STX,int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12)
BEGIN--決定轉(zhuǎn)換狀態(tài)的進程
CASE STX IS
WHEN st0 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st1 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st2 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st3 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st4 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st5 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st6 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st7 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN OTHERS => NULL;
END CASE;
END PROCESS COM1;REG: PROCESS(clk,Reset,sel)
--主控時序進程
BEGIN
IF Reset = '1' THEN
STX<= st0;
--異步復(fù)位
ELSIF clk='1' AND clk'EVENT THEN
if sel='1' then
CASE STX IS
WHEN st0=>STX<=st1;
WHEN st1=>STX<=st2;
WHEN st2=>STX<=st3;
WHEN st3=>STX<=st4;
WHEN st4=>STX<=st5;
WHEN st5=>STX<=st6;
WHEN st6=>STX<=st7;
WHEN st7=>STX<=st0;
END CASE;
END IF;
END if;END PROCESS;
2、顯示切換程序 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux1 is
Port(clk,ina,inb,sel,Reset : in std_logic;
result : out std_logic);end mux1;
architecture Behavioral of mux1 is
TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);
SIGNAL STX:state;begin REG1: PROCESS(ina,inb,STX)
BEGIN
CASE STX IS
WHEN st0=>result<=ina;
WHEN st1=>result<=ina;
WHEN st2=>result<=inb;
WHEN st3=>result<=inb;
WHEN st4=>result<=inb;
WHEN st5=>result<=inb;
WHEN st6=>result<=inb;
WHEN st7=>result<=inb;
END CASE;
END PROCESS;REG2:PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN
STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN
if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;
END CASE;END IF;end if;END PROCESS REG2;
end Behavioral;
3、置數(shù)操作模塊
運用狀態(tài)機，進行置數(shù)操作 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux is
Port(clk,ina,inb,sel,Reset : in std_logic;
r1,r2,r3,r4,r5,r6 : out std_logic);end mux;
architecture Behavioral of mux is TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);
SIGNAL STX:state;begin PROCESS(ina,inb,STX)BEGIN CASE STX IS WHEN st0=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st1=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st2=>r1<='0';r2<='0';r3<='0';r4<='0';r5<='0';r6<=inb;WHEN st3=>r1<='0';r2<='0';r3<='0';r4<='0';r5<=inb;r6<='0';WHEN st4=>r1<='0';r2<='0';r3<='0';r4<=inb;r5<='0';r6<='0';WHEN st5=>r1<='0';r2<='0';r3<=inb;r4<='0';r5<='0';r6<='0';WHEN st6=>r1<='0';r2<=inb;r3<='0';r4<='0';r5<='0';r6<='0';WHEN st7=>r1<=inb;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';END CASE;END PROCESS;PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;
END CASE;END IF;end if;END PROCESS;end Behavioral;end Behavioral;
4、秒顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity secute1 is
Port(clkm,set,reset : in std_logic;
sec2,sec1 : inout std_logic_vector(3 downto 0);
ensec : out std_logic);end secute1;
architecture Behavioral of secute1 is
begin
Process(clkm,reset,set)
Begin
If reset='1' then sec2<=“0000”;sec1<=“0000”;
Elsif set='1' then sec2<=“0101”;sec1<=“1000”;
Elsif(clkm'event and clkm='1')then
if sec2=“0101” AND sec1=“1001” then sec2<=“0000”;sec1<=“0000”;ensec<='1';
elsif sec1=“1001” then sec2<=sec2+'1';sec1<=“0000”;ensec<='0';
else sec1<=sec1+'1';ensec<='0';
end if;end if;End process;end Behavioral;
5、分顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity minute1 is
Port(clkm,set,reset : in std_logic;
min2,min1 : inout std_logic_vector(3 downto 0);
enmin : out std_logic);end minute1;
architecture Behavioral of minute1 is
begin
Process(clkm,reset,set)
Begin
If reset='1' then min2<=“0000”;min1<=“0000”;
Elsif set='1' then min2<=“0101”;min1<=“1000”;
Elsif(clkm'event and clkm='1')then
if min2=“0101” AND min1=“1001” then min2<=“0000”;min1<=“0000”;enmin<='1';
elsif min1=“1001” then min2<=min2+'1';min1<=“0000”;enmin<='0';
else min1<=min1+'1';enmin<='0';
end if;end if;End process;end Behavioral;
6、小時顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity hour1 is
Port(clkh,set,reset: in std_logic;
hor2,hor1 : inout std_logic_vector(3 downto 0);
enhour : out std_logic);end hour1;
architecture Behavioral of hour1 is
begin Process(clkh,reset,set)
Begin
If reset='1' then hor2<=“0000”;hor1<=“0000”;
Elsif set='1' then hor2<=“0010”;hor1<=“0011”;
Elsif(clkh'event and clkh='1')then
if hor2=“0010” AND hor1=“0011” then hor2<=“0000”;hor1<=“0000”;enhour<='1';
elsif hor1=“1001” then hor2<=hor2+'1';hor1<=“0000”;enhour<='0';
else hor1<=hor1+'1';enhour<='0';
end if;
end if;End process;end Behavioral;
7、日顯示模塊（已加入閏年判斷功能）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity date1 is
Port(clkd,set : in std_logic;
dat2,dat1 : inout std_logic_vector(3 downto 0);
endate : out std_logic);end date1;
architecture Behavioral of date1 is
begin
Process(clkd,set)
Begin
if set='1' then dat2<=“0010”;dat1<=“1000”;
Elsif(clkd'event and clkd='1')then
if dat2=“0011” AND dat1=“0000” then dat2<=“0000”;dat1<=“0001”;endate<='1';elsif dat1=“1001” then dat2<=dat2+'1';dat1<=“0000”;endate<='0';
else dat1<=dat1+'1';endate<='0';
end if;end if;End process;end Behavioral;
8、月顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity month1 is
Port(clkn,set: in std_logic;
mon2,mon1 : inout std_logic_vector(3 downto 0);
enmon : out std_logic);end month1;
architecture Behavioral of month1 is
begin
Process(clkn,set)
Begin
if set='1' then mon2<=“0000”;mon1<=“0110”;
Elsif(clkn'event and clkn='1')then
if mon2=“0001” AND mon1=“0010” then mon2<=“0000”;mon1<=“0001”;enmon<='1';
elsif mon1=“1001” then mon2<=mon2+'1';mon1<=“0000”;enmon<='0';
else mon1<=mon1+'1';enmon<='0';
end if;end if;End process;
9、年顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity yearth1 is
Port(clkn,set: in std_logic;
year2,year1 : inout std_logic_vector(3 downto 0);
enyear : out std_logic);end yearth1;
architecture Behavioral of yearth1 is
begin
Process(clkn,set)
Begin
if set='1' then year2<=“0001”;year1<=“0001”;
Elsif(clkn'event and clkn='1')then
if year2=“1001” AND year1=“1001” then year2<=“0000”;year1<=“0001”;
elsif year1=“1001” then year2<=year2+'1';year1<=“0000”;enyear<='0';
else year1<=year1+'1';enyear<='0';
end if;end if;
end Behavioral;
第三篇：多功能數(shù)字鐘課程設(shè)計整點報時與鬧鐘功能VHDL代碼
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity timkeeper is
Port(up,setpin,upclk,settime,run : in std_logic;
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0);
result: out std_logic);end timkeeper;
architecture Behavioral of timkeeper is
component h_m_s_time port（clk0,clk1,ce : in std_logic;
sec0,sec1 : buffer std_logic_vector(3 downto 0);
lock : in std_logic_vector(2 downto 0);
up : in std_logic;min0,min1 : buffer std_logic_vector(3 downto 0);hour0,hour1 : buffer std_logic_vector(3 downto 0);ov : out std_logic);end component;component date port（clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
date0,date1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);
end component;component month_year port（clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1 : buffer std_logic_vector(3 downto 0);
year0,year1 : buffer std_logic_vector(3 downto 0));end component;component LED_disp port（lock : in std_logic_vector(2 downto 0);
sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);
date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end component;component alarm Port（hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
settime,run : in std_logic;
result : out std_logic);end component;
signal Tlock:std_logic_vector(2 downto 0);signal Tsecond_wave:std_logic;signal Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1:std_logic_vector(3 downto 0);signal Tdate0,Tdate1,Tmon0,Tmon1,Tyear0,Tyear1:std_logic_vector(3 downto 0);signal Tovday,Tovmonth:std_logic;signal vcc:std_logic;begin vcc<='1';process(setpin)begin
if rising_edge(setpin)then
Tlock<=Tlock+'1';
end if;
end process;
u2:h_m_s_time port map(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up，Tmin0,Tmin1,Thour0,Thour1,Tovday);u3:date port map(Tovday,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1，Tdate0,Tdate1,Tovmonth);u4:month_year port map(Tovmonth,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1);u5:LED_disp port map(Tlock,Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,Tdate0，Tdate1,Tmon0,Tmon1,Tyear0,Tyear1,a0,a1,b0,b1,c0,c1);u6:alarm port map(Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,settime,run ,result);end Behavioral;
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity alarm is
Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
settime,run : in std_logic;
result : out std_logic);end alarm;
architecture Behavioral of alarm is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(settime)
begin
if settime='1'then
dhour1<=hour1;
dhour0<=hour0;
dmin1<=min1;
dmin0<=min0;
dsec1<=sec1;
dsec0<=sec0;
end if;
end process p0;p1:process(run)
begin if run='1'then
if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then
result<='1';
else result<='0';
end if;else result<='0';end if;
end process p1;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity date is
Port(clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
date0,date1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);end date;
architecture Behavioral of date is signal tempy0:std_logic_vector(1 downto 0);signal tempy1,clk:std_logic;signal Td0,Td1:std_logic_vector(3 downto 0);begin tempy0<=year0(1 downto 0);tempy1<=year1(0);Td0<=date0;Td1<=date1;u1:process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then clk<=clk0;
else clk<=clk1;
end if;
end process u1;
u2:process(clk,ce)
begin
if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“100” and up='1')then
if(mon0=“0010” and mon1=“0000”)then
Feb_add_day(Td0,Td1,tempy0,tempy1,date0,date1);
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and or(mon0=“0101” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)
mon1=“0000”)
or(mon0=“1000” and mon1=“0000”)or(mon0=“0000”and mon1=“0001”)or(mon0=“0010” and mon1=“0001”))then
oddmonth_add_day(Td0,Td1,date0,date1);
else evenmonth_add_day(Td0,Td1,date0,date1);
end if;
end if;
if(lock=“100” and up='0')then
if(mon0=“0010” and mon1=“0000”)then
Feb_sub_day(Td0,Td1,tempy0,tempy1,date0,date1);
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0101” and mon1=“0000”)or
(mon0=“0111” and mon1=“0000”)or(mon0=“1000” and mon1=“0000”)or(mon0=“0000” and mon1=“0001”)or(mon0=“0010”
and mon1=“0001”))then
oddmonth_sub_day(Td0,Td1,date0,date1);
else evenmonth_sub_day(Td0,Td1,date0,date1);
end if;
end if;
end if;
end if;
end process u2;
u3:process(ce)
begin
if rising_edge(clk)then
if(lock/=“000” and lock/=“001”)then
ov<='0';
elsif(ce='1')then
if(mon0=“0010” and mon1=“0000”)then
if((tempy1='0' and tempy0=“00”)or(tempy1='1' and tempy0=“10”))then
if(date0=“1001” and date1=“0010”)then
ov<='1';
else ov<='0';
end if;
elsif(date0=“1000” and date1=“0010”)then ov<='1';else ov<='0';end if;
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0010” and mon1=“0000”)
or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” or(mon0=“0000” and mon1=“0001”)
or(mon0=“0010” and mon1=“0001”))then
if(date0=“0001” and date1=“0011”)then
ov<='1';
else ov<='0';
end if;
elsif(date0=“0000” and date1=“0011”)then
ov<='1';
else ov<='0';
end if;
end if;
end if;
end process u3;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;
and
mon1=“0000”)use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity h_m_s_time is
Port(clk0,clk1,ce : in std_logic;
sec0,sec1 : buffer std_logic_vector(3 downto 0);
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
min0,min1 : buffer std_logic_vector(3 downto 0);
hour0,hour1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);end h_m_s_time;
architecture Behavioral of h_m_s_time is signal Ts0,Ts1,Tm0,Tm1,Th0,Th1:std_logic_vector(3 downto 0);signal clk:std_logic;begin
Ts0<=sec0;Ts1<=sec1;Tm0<=min0;Tm1<=min1;Th0<=hour0;Th1<=hour1;u1: process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then
clk<=clk0;
else clk<=clk1;
end if;
end process u1;
u2: process(clk,lock)
begin
if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“111” and up='1')then
addsec_addmin(Ts0,Ts1,sec0,sec1);
end if;
if(lock=“111” and up='0')then
subsec_submin(Ts0,Ts1,sec0,sec1);
end if;
if(lock=“000” or lock=“001”)then
if(sec0=“1001” and sec1=“0101”)then
addsec_addmin(Tm0,Tm1,min0,min1);
end if;
if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”)then
addhour(Th0,Th1,hour0,hour1);
end if;
if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”
and hour0=“0011” and hour1=“0010”)then
ov<='1';
else ov<='0';
end if;
end if;
if(lock=“110” and up='1')then
addsec_addmin(Tm0,Tm1,min0,min1);
end if;
if(lock=“101” and up='0')then
subsec_submin(Tm0,Tm1,min0,min1);
end if;
if(lock=“101” and up='1')then
addhour(Th0,Th1,hour0,hour1);
end if;
if(lock=“101” and up='0')then
subhour(Th0,Th1,hour0,hour1);
end if;
end if;
end if;
end process u2;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity LED_disp is
Port(lock : in std_logic_vector(2 downto 0);
sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);
date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end LED_disp;
architecture Behavioral of LED_disp is begin process(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1)
begin
if(lock=“000”)then
a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;
end if;
if(lock=“000”)then
a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;
end if;
if(lock=“001”)then
a0<=date0;a1<=date1;b0<=mon0;b1<=mon1;c0<=year0;c1<=year1;
end if;
if(lock=“101”)then
a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=hour0;c1<=hour1;
end if;
if(lock=“110”)then
a0<=“0000”;a1<=“0000”;b0<=min0;b1<=min1;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“111”)then
a0<=sec0;a1<=sec1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“010”)then a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=year0;c1<=year1;end if;if(lock=“011”)then
a0<=“0000”;a1<=“0000”;b0<=mon0;b1<=mon1;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“100”)then
a0<=date0;a1<=date1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;
end if;
end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity month_year is
Port(clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1 : buffer std_logic_vector(3 downto 0);
year0,year1 : buffer std_logic_vector(3 downto 0));end month_year;
architecture Behavioral of month_year is signal Ty0,Ty1,Tm0,Tm1:std_logic_vector(3 downto 0);signal clk:std_logic;begin
Ty0<=year0;Ty1<=year1;Tm0<=mon0;Tm1<=mon1;u1: process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then
clk<=clk0;
else clk<=clk1;
end if;
end process u1;u2:process(clk,ce)begin if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“011” and up='1')then
add_month(Tm0,Tm1,mon0,mon1);
end if;
if(lock=“011” and up='0')then
sub_month(Tm0,Tm1,mon0,mon1);
end if;
if(lock=“000” or lock=“001”)then
if(mon0=“0010” and mon1=“0001”)then
add_year(Ty0,Ty1,year0,year1);
end if;
end if;
if(lock=“010” and up='1')then
add_year(Ty0,Ty1,year0,year1);
end if;
if(lock=“010” and up='0')then
sub_year(Ty0,Ty1,year0,year1);
end if;
end if;
end if;
end process u2;
end Behavioral;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
package pac is
procedure add_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector);procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector);procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector);procedure sub_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector);procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;
ty0:in std_logic_vector(1 downto 0);
ty1:in std_logic;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;
ty0:in std_logic_vector(1 downto 0);
ty1:in std_logic;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector);procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector);procedure addhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector);procedure subhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector);end pac;package body pac IS procedure add_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector)is
begin
if(oldyear0=“1001” and oldyear1/=“1001”)then
newyear0<=“0000”;newyear1<=oldyear1+'1';
else newyear0<=oldyear0+'1';
end if;if oldyear0=“1001” and oldyear1=“1001” then newyear0<=“0000”;
newyear1<=“0000”;end if;end add_year;
procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector)is
begin
if oldmonth0=“0010” and oldmonth1=“0001” then newmonth0<=“0001”;
newmonth1<=“0000”;
elsif oldmonth0=“1001” then newmonth0<=“0000”;
newmonth1<=oldmonth1+'1';else
newmonth0<=oldmonth0+'1';end if;end add_month;procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;signal newmonth1: out std_logic_vector)is begin
if oldmonth0=“0001”and oldmonth1=“0000”then
newmonth0<=“0010”;newmonth1<=“0001”;
elsif oldmonth0=“0000” and oldmonth1=“0001” then
newmonth0<=“1001”;newmonth1<= oldmonth1-'1';else newmonth0<=oldmonth0-'1';end if;if oldmonth0=“0000” and oldmonth1=“0000”then
newmonth0<=“0010”;newmonth1<=“0001”;
end if;
end sub_month;procedure sub_year(oldyear0,oldyear1:in std_logic_vector;signal newyear0: out std_logic_vector;signal newyear1: out std_logic_vector)is
begin if oldyear0=“0000”then
if oldyear1=“0000”then
newyear1<=“1001”;else newyear1<= oldyear1-'1';end if;newyear0<=“1001”;else newyear0<=oldyear0-'1';end if;end sub_year;procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;
Ty0:in std_logic_vector(1 downto 0);
Ty1:in std_logic;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if oldday0=“1000”and oldday1=“0010”then
if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then
newday0<=oldday0 +'1';else newday0<=“0001”;newday1<=“0000”;end if;elsif oldday0=“1001” and oldday1=“0010”then
newday0<=“0001”;newday1<=“0000”;elsif oldday0=“1001” then
newday0<=“0000”;newday1<=oldday1+'1';else newday0<=oldday0+'1';end if;end Feb_add_day;
procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;
Ty0:in std_logic_vector(1 downto 0);
Ty1:in std_logic;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then
if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then
newday0<=“1001”;newday1<=“0010”;
else newday0<=“1000”;newday1<=“0010”;
end if;
elsif oldday0=“0000” and oldday1/=“0000”then
newday0<=“1001”;newday1<=oldday1-'1';else newday0<=oldday0-'1';end if;end Feb_sub_day;procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0001” and oldday1=“0011”)then
newday0<=“0001”;newday1<=“0000”;
elsif oldday0=“1001”then
newday0<=“0000”;newday1<=oldday1+'1';
else newday0<= oldday0+'1';
end if;
end oddmonth_add_day;procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0001” or oldday0=“0000”)and oldday1=“0000” then
newday0<=“0001”;newday1<=“0011”;
elsif oldday0=“0000” and oldday1/=“0000” then
newday0<=“1001”;newday1<=oldday1-'1';
else newday0<= oldday0-'1';
end if;
end oddmonth_sub_day;procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if oldday0=“0000” and oldday1=“0011” then newday0<=“0001”;
newday1<=“0000”;
elsif oldday0=“1001”then
newday0<=“0000”;
newday1<=oldday1+'1';
else newday0<=oldday0+'1';
end if;
end evenmonth_add_day;procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector)is begin
if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then
newday0<=“0000”;
newday1<=“0011”;elsif oldday0=“0000” and oldday1/=“0000”
then newday0<=“1001”;
newday1<=oldday1-'1';else
newday0<=oldday0-'1';
end if;end
evenmonth_sub_day;
procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector)is
begin
if
(oldtime0=“1001”)then
newtime0<=“0000”;
if(oldtime1=“0101”)then
newtime1<=“0000”;
else newtime1<=oldtime1+'1';
end if;
else newtime0<=oldtime0+'1';
end if;
end addsec_addmin;procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector)is begin
if(oldtime0=“0000”)then
newtime0<=“1001”;
if(oldtime1=“0000”)then
newtime1<=“0101”;
else newtime1<=oldtime1-'1';
end if;
else newtime0<=oldtime0-'1';
end if;
end
subsec_submin;procedure addhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector)is begin
if(oldhour0=“1001”)then
newhour0<=“0000”;
newhour1<=oldhour1+'1';
else newhour0<=oldhour0+'1';
end if;
if oldhour0=“0011” and oldhour1=“0010”then
newhour0<=“0000”;newhour1<=“0000”;
end if;
end
addhour;procedure subhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector)is begin if oldhour0=“0000” then
newhour1<=oldhour1-'1';newhour0<=“1001”;
else newhour0<=oldhour0-'1';
end if;
if oldhour0=“0000” and oldhour1=“0000”then
newhour0<=“0011”;newhour1<=“0010”;
end if;
end
subhour;end pac;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity second_wave is
Port(f1000 : in std_logic;
second_wave1 : buffer std_logic);end second_wave;
architecture Behavioral of second_wave is signal cnt:std_logic_vector(8 downto 0);begin
process(f1000,cnt)
begin
if rising_edge(f1000)then
if(cnt=“111110011”)then
cnt<=“000000000”;second_wave1<=not second_wave1;
else cnt<=cnt+'1';
end if;
end if;
end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity settime is
Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
mytime,run : in std_logic;
result : out std_logic);end settime;
architecture Behavioral of settime is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(mytime)
begin
if mytime='1'then
dhour1<=hour1;
dhour0<=hour0;
dmin1<=min1;
dmin0<=min0;
dsec1<=sec1;
dsec0<=sec0;
end if;
end process p0;p1:process(run)
begin if run='1'then
if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then
result<='1';
else result<='0';
end if;else result<='0';end if;
end process p1;end Behavioral;
第四篇：多功能數(shù)字鐘課程設(shè)計
多功能數(shù)字鐘
朱安煙
（安陽師范學(xué)院 物電學(xué)院, 河南 安陽 455002）
摘要：時鐘相比具有更高的準(zhǔn)確性和直觀性
因此得到了更加廣泛的使用。數(shù)字鐘從原理上講是一種典型的數(shù)字電路，其中
本設(shè)計采用六位LED
24小時計時方式根據(jù)數(shù)碼管動態(tài)顯示原理來進行顯示。用晶振產(chǎn)生振蕩脈加以分頻得到所需的鐘表秒脈沖,利用純數(shù)字電路，實現(xiàn)數(shù)字電子時鐘功能,時間重置功能。此次數(shù)字鐘的理圖設(shè)計，PCB圖的制作主要是基于altium designer軟件，利用proteus7.7軟件進行仿真，最終本設(shè)計實現(xiàn)24小時的時鐘計時、時間重置功能。
關(guān)鍵詞：LED數(shù)碼管
時序電路
邏輯電路
時鐘
校時引言
僅向。方案論證：
2.1方案一
由于是數(shù)字鐘的設(shè)計，可以用單片機AT89C51來實現(xiàn)計數(shù)功能，相對于純數(shù)字電路來講它具有功耗低、體積小、使用方便等優(yōu)點。但在大二下半學(xué)期初期，對單片機方面的內(nèi)容知識還不夠完善，加上用單片機為核心來做數(shù)字鐘還需做編程，對自身來說又是一難點。不過此法可以待以后，學(xué)習(xí)知識完善后再考慮。
2.2 方案二
繼而考慮到用原先學(xué)過的純數(shù)字電路來做，以74Ls160來做為計數(shù)的芯片，用六片分別實現(xiàn) 數(shù)字鐘的小時、分、秒、的計數(shù)，并用晶振加以分頻產(chǎn)生數(shù)字鐘所需的秒脈沖。
從以上兩種方案，很容易看出，采用方案二，用此法做即可以復(fù)習(xí)回顧早期學(xué)習(xí)的數(shù)電模電知識，又避免了單片機知識不足的問題，故用此法。結(jié)果與討論
3.1.1數(shù)字鐘主要計數(shù)芯片為74ls160其引腳圖如下：
這種同步可預(yù)置十進計數(shù)器是由四個D型觸發(fā)器和若干個門電路構(gòu)成，內(nèi)部有超前進位，具有計數(shù)、置數(shù)、禁止、直接（異步）清零等功能。對所有觸發(fā)器同時加上時鐘，使得當(dāng)計數(shù)使能輸入和內(nèi)部門發(fā)出指令時輸出變化彼此協(xié)調(diào)一致而實現(xiàn)同步工作。這種工作方式消除了非同步（脈沖時鐘）計數(shù)器中常有的輸出計數(shù)尖峰。緩沖時鐘輸入將在時鐘輸入上升沿觸發(fā)四個觸發(fā)器。這種計數(shù)器是可全編程的，即輸出可預(yù)置到任何電平。當(dāng)預(yù)置是同步時，在置數(shù)輸入上將建立一低電平，禁止計數(shù)，并在下一個時鐘之后不管使能輸入是何電平，輸出都與建立數(shù)據(jù)一致。清除是異步的（直接清零），不管時鐘輸入、置數(shù)輸入、使能輸入為何電平，清除輸入端的低電平把所有四個觸發(fā)器的輸出直接置為低電平。超前進位電路無須另加門，即可級聯(lián)出n位同步應(yīng)用的計數(shù)器。它是借助于兩個計數(shù)使能輸入和一個動態(tài)進位輸出來實現(xiàn)的。兩個計數(shù)使能輸入（ENP和ENT）計數(shù)時必須是高電平，且輸入ENT必須正反饋，以便使能動態(tài)進位輸出。因而被使能的動態(tài)進位輸出將產(chǎn)生一個高電平輸出脈沖，其寬度近似等于QA輸出高電平。此高電平溢出進位脈沖可用來使能其后的各個串聯(lián)級。使能ENP和ENT輸入的跳變不受時鐘輸入的影響。電路有全獨立的時鐘電路。改變工作模式的控制輸入（使能ENP、ENT或清零）縱使發(fā)生變化，直到時鐘發(fā)生為止，都沒有什么影響。計數(shù)器的功能（不管使能、不使能、置數(shù)或計數(shù)）完全由穩(wěn)態(tài)建立時間和保持時間所要求的條件來決定。
管腳說明： CLR:清零復(fù)位端
當(dāng)輸入為低電平時有效
CLK：時鐘信號接收端
A~D:讀入
QA~QD:輸出
ENT、ENP置一時芯片正常工作
LOAD:置數(shù)端
RCO：信號輸出端
GND：接地
Vcc：接高
工作方式：
3.1.2 7段LED數(shù)碼管
3.1.3 32.768KHZ晶振
32.768KHZ是一個標(biāo)準(zhǔn)的頻率，晶振頻率的應(yīng)用主要有以下幾個方面的參數(shù)：尺寸、負載電容、頻率偏差、應(yīng)用范圍。按尺寸外形來分主要分為插件和貼片的；插件的主要有2*
6、3*
8、49s 等，貼片的就有很多種了，跟據(jù)各公司的設(shè)計可的型號有很多，例如：日本KDS晶振就有49SMD、DST310S、SM—14J、DST520、DST410S等。
3.1.4 CD4060分頻器
CD4060由一振蕩器和14級二進制串行計數(shù)器位組成，振蕩器的結(jié)構(gòu)可以是RC或晶振電路，CR為高電平時，計數(shù)器清零且振蕩器使用無效。所有的計數(shù)器位均為主從觸發(fā)器。在CP1(和CP0)的下降沿計數(shù)器以二進制進行計數(shù)。在時鐘脈沖線上使用斯密特觸發(fā)器對時鐘上升和下降時間無限制 引腳功能：
/CP1：時鐘輸入端
/CP0：時鐘輸出端
/CP0：反相時鐘輸出端
Q4~Q10，Q12~Q14：計數(shù)器輸出端
/Q14：第14級計數(shù)器反相輸出端
VDD：電源正
VSS：電源負
CR：清零端 3.1.5 74ls48
功能介紹：
74LS48除了有實現(xiàn)7段顯示譯碼器基本功能的輸入（DCBA）和輸出（Ya～Yg）端外，7448還引入了燈測試輸入端（LT）和動態(tài)滅零輸入端（RBI），以及既有輸入功能又有輸出功能的消隱輸入/動態(tài)滅零輸出（BI/RBO）端。
由7448真值表可獲知7448所具有的邏輯功能：
（1）7段譯碼功能（LT=1，RBI=1）
在燈測試輸入端（LT）和動態(tài)滅零輸入端（RBI）都接無效電平時，輸入DCBA經(jīng)7448譯碼，輸出高電平有效的7段字符顯示器的驅(qū)動信號，顯示相應(yīng)字符。除DCBA = 0000外，RBI也可以接低電平，見表1中1～16行。
（2）消隱功能（BI=0）
此時BI/RBO端作為輸入端，該端輸入低電平信號時，表1倒數(shù)第3行，無論LT 和RBI輸入什么電平信號，不管輸入DCBA為什么狀態(tài)，輸出全為“0”，7段顯示器熄滅。該功能主要用于多顯示器的動態(tài)顯示。
（3）燈測試功能（LT = 0）
此時BI/RBO端作為輸出端，端輸入低電平信號時，表1最后一行，與 及DCBA輸入無關(guān)，輸出全為“1”，顯示器7個字段都點亮。該功能用于7段顯示器測試，判別是否有損壞的字段。
（4）動態(tài)滅零功能（LT=1，RBI=1）
此時BI/RBO端也作為輸出端，LT 端輸入高電平信號，RBI 端輸入低電平信號，若此時DCBA = 0000，表1倒數(shù)第2行，輸出全為“0”，顯示器熄滅，不顯示這個零。DCBA≠0，則對顯示無影響。該功能主要用于多個7段顯示器同時顯示時熄滅高位的零。
3.2 原理設(shè)計
整體電路設(shè)計方案：
3.2.1 振蕩電路設(shè)計
振蕩電路由振蕩器產(chǎn)生的脈沖，振蕩器是數(shù)字鐘的核心。振蕩器的穩(wěn)定度及頻率的精度決定了數(shù)字鐘的精確程度，次處有555定時器和晶振兩種產(chǎn)生秒脈沖的方法：555振蕩器做振蕩源一般用于精確度要求不高的場合，由門電路組成的多諧振蕩器的振蕩周期不僅與時間常數(shù)RC有關(guān)，而且還取決于門電路的閾值電壓VTH，由于VTH容易受到溫度、電源電壓及干擾的影響，因此頻率穩(wěn)定性較差，只能用于對頻率穩(wěn)定性要求不高的場合。考慮到振蕩頻率的精確度與穩(wěn)定性固采用晶振做為振蕩源來實現(xiàn)振蕩電路，得時鐘脈沖更穩(wěn)定，時間走的更準(zhǔn)37.268KHz晶振 通過cd4060分頻器進行十四分頻得到0.5s的脈沖信號，再進行一個SN74LS74進行二分頻得到所需的秒脈沖信號：
3.2.2 校時電路設(shè)計
根據(jù)電路設(shè)計所知需要在分處和小時處需要校時，分別在分和時個位向十位進位處各加一開關(guān)，另一端接地并且在與地之間接100pf電容為防止按鍵抖動。
電路設(shè)計如下：
當(dāng)開關(guān)處于自然位置時分十位clk端所接為高電平，當(dāng)開關(guān)按下時則引入一低電平實其clk端有一個下降沿脈沖接入，使其產(chǎn)生了校時功能。
3.2.3顯示電路設(shè)計
顯示電路是用74ls48驅(qū)動七段共陰數(shù)碼管來作為時鐘顯示器。
電路設(shè)計如下：
3.2.4 計時電路設(shè)計
數(shù)字鐘的秒和分位都是從0到60循環(huán)計數(shù)的，所以可以用用異步清零法設(shè)計60進制計數(shù)器作為秒和分的計數(shù)器。用異步置數(shù)法設(shè)計小時所用的24進制計數(shù)器。秒、分位設(shè)計電路如下：
3.3 程序調(diào)試過程
在板子焊接好以后通上5V電源發(fā)現(xiàn)六Led燈只有三個能完整亮出來，其余的都不亮或是亮的不全，而且秒位不走，校時按鍵不管用。問題很多。
開始調(diào)試：
1、首先調(diào)試的是秒位為何不走，先測晶振石否起振，測量后發(fā)現(xiàn)晶振正常起振，然后從74ls160的clk端用示波器測試一下沒有脈沖信號輸入，則找74ls74的輸出口也無脈沖，以次往前推，最后測量出從74ls74輸入端有正確的脈沖輸入，輸出端卻無脈沖輸出。觀察后沒有連接錯誤，故用萬用表測vcc.end端都有正確的電平接入，再測量兩點間是否有漏焊現(xiàn)象，最后測出一處漏焊點使D端與Q端沒有接通。重新焊接后秒位正常計時。
2、秒位正常計時，但向秒的十位進位時總是顯示從8到19，查閱資料可知，在第一個160芯片到第二個160芯片中缺一個非門，充當(dāng)延時作用，使個位計數(shù)到9再來一個脈沖下計數(shù)時再向前進位。加上非門進位正常了。
3、秒位向分位進位正常，但校時按鍵不能用，且分位向十分位不能進位，通過觀察焊接對比原理圖與pcb圖后發(fā)現(xiàn)，開關(guān)接地的一端弄反了，應(yīng)是開關(guān)與接電容端相側(cè)對著的端接地。這個錯誤導(dǎo)致開關(guān)不能用，亦使分的十位端的74ls160芯片clk段一直接了地，故不能使其正常進位。修改過后則可以正常進位，且兩開關(guān)都能用了。
4、顯示小時位的第一個數(shù)碼管一直不亮，通過測量發(fā)現(xiàn)led數(shù)碼管沒有燒壞，能正常工作，通過對比PCB圖觀察沒有焊接錯誤，用萬用表測量則發(fā)現(xiàn)驅(qū)動次led的74ls48管沒有正常接地，連接跳線處有一虛焊，重新焊接后恢復(fù)正常。
5、但分向小時不能進位，由示波器觀察發(fā)現(xiàn)74ls160芯片clk端無脈沖輸入，但十分位有脈沖輸出，且導(dǎo)線也導(dǎo)通了，就觀察原理圖發(fā)現(xiàn)原理圖一處錯誤，分向時進位時是分滿60向前進一個脈沖，故分的TC端不用再接到時的CLK端了。找到錯誤后用鑷子將板上的銅線劃段，則正常進位了。
6、小時進位正常但顯示的不是24進制，顯示的是44進制，則推測可能是跳線連接錯誤，將顯示小時的十位 74ls160芯片接B端連接成接C端了，故使其顯示44進制，通過觀察、對比pcb圖，最后發(fā)現(xiàn)果然如此。修改過后小時為正常24進制了。
7、最后一個數(shù)碼管有三段老是不亮，觀察連接沒有錯誤，測量焊接也正常，最后用萬用表測量發(fā)現(xiàn)芯片沒有問題，那三段不亮的數(shù)碼管燒了。
8、調(diào)試好后在后來的觀察中發(fā)現(xiàn)從秒向分進位時有時一下進兩位，自己找不出來原因。問過老師后，老師說是由于防抖電容所致。嘗試著將電容先劃斷試了一下就沒有那種情況了。但此時校時開關(guān)由于抖動緣故，按一下有時跳3、4個位，校時不穩(wěn)定了。結(jié)論
此數(shù)字鐘相對于機械鐘來說有低功耗，高精度，數(shù)字化顯示和不易損壞等特點。符合人們?nèi)粘＜揖蛹稗k公對鐘表的要求，可以作為家居、辦公等用表。
參考文獻
[1] 佘新平數(shù)學(xué)電子技術(shù)基礎(chǔ) 華中科技大學(xué)出版社 2009年
[2] 許樹玲 丁電寬 王晉 電子技術(shù)及實驗 內(nèi)蒙古大學(xué)出版社2005年
[3] 佘新平數(shù)字電路設(shè)計·仿真·測試 華中大學(xué)出版社 2010年
附圖: 電路原理圖:
第五篇：多功能數(shù)字鐘課程設(shè)計報告
課題名稱 姓名 學(xué)號 院、系、部 專業(yè) 指導(dǎo)教師
電子技術(shù)課程設(shè)計報告書
2016年6月12日
一、設(shè)計任務(wù)及要求：
用中小規(guī)模集成芯片設(shè)計并制作多功能數(shù)字鐘，具體要求如下：
1、準(zhǔn)確及時，以數(shù)字形式顯示時（00～23）、分（00～59）、秒（00～59）的時間。
2、具有校時功能。指導(dǎo)教師簽名：
2016
二、指導(dǎo)教師評語：
指導(dǎo)教師簽名：
2016
三、成績
指導(dǎo)教師簽名：
2016年6月年6月年6月日
日
日
多功能數(shù)字鐘課程設(shè)計報告 設(shè)計目的
一、設(shè)計原理與技術(shù)方法：
包括：電路工作原理分析與原理圖、元器件選擇與參數(shù)計算、電路調(diào)試方法與結(jié)果說明； 軟件設(shè)計說明書與流程圖、軟件源程序代碼、軟件調(diào)試方法與運行結(jié)果說明。
1、電路工作原理分析與原理圖
數(shù)字鐘實際上是一個對標(biāo)準(zhǔn)頻率（1Hz）進行計數(shù)的計數(shù)電路。由于標(biāo)準(zhǔn)的1Hz 時間信號必須做到準(zhǔn)確穩(wěn)定，所以通常使用輸出頻率穩(wěn)定的石英晶體振蕩器電路構(gòu)成數(shù)字鐘的振源。又由于計數(shù)的起始時間不可能與標(biāo)準(zhǔn)時間（如北京時間）一致，故需要在電路上加一個校時電路。因此一個具有計時、校時、報時、顯示等基本功能的數(shù)字鐘主要由振蕩器、分頻器、計數(shù)器、譯碼器、顯示器、校時電路、報時電路等七部分組成。石英晶體振蕩器產(chǎn)生的信號經(jīng)過分頻器得到秒脈沖后，秒脈沖送入計數(shù)器計數(shù)，計數(shù)結(jié)果通過“時”、“分”、“秒”譯碼器譯碼，并通過顯示器顯示時間。由以上分析可得到原理框圖如下圖
圖1 實驗原理框圖
2、元器件選擇與參數(shù)計算
（1）晶體振蕩電路：產(chǎn)生秒脈沖既可以采用555脈沖發(fā)生電路也可以采用晶振脈沖發(fā)生電路。若由集成電路定時器555與RC組成的多諧振蕩器作為時間標(biāo)準(zhǔn)信號源，可使555與RC組成多諧振蕩器，產(chǎn)生頻率 f=1kHz的方波信號，再通過分頻則可得到秒脈沖信號。晶體振蕩器電路則可以給數(shù)字鐘提供一個頻率穩(wěn)定準(zhǔn)確的32768Hz的方波信號，可保證數(shù)字鐘的走時準(zhǔn)確及穩(wěn)定。相比二者的穩(wěn)定性，晶振電路比555電路能夠產(chǎn)生更加穩(wěn)定的脈沖，數(shù)字電路中的時鐘是由振蕩器產(chǎn)生的，振蕩器是數(shù)字鐘的核心。振蕩器的穩(wěn)定度及頻率的精度決定了數(shù)字鐘計時的準(zhǔn)確程度，所以最后決定采用晶振脈沖發(fā)生電路。石英晶體振蕩器的特點是振蕩頻率準(zhǔn)確、電路結(jié)構(gòu)簡單、頻率易調(diào)整，它是電子鐘的核心，用它產(chǎn)生標(biāo)準(zhǔn)頻率信號，再由分頻器分成秒時間脈沖。
所以秒脈沖晶體振蕩選用32768Hz的晶振，該元件專為數(shù)字鐘電路而設(shè)計，其頻率較低，有利于減少分頻器級數(shù)。從有關(guān)手冊中，可查得C1、C2均為20pF。當(dāng)要求頻率準(zhǔn)確度和穩(wěn)定度更高時，還可接入校正電容并采取溫度補償措施。由于CMOS電路的輸入阻抗極高，因此反饋電阻R1可選為20MΩ。
（2）分頻器電路：分頻器電路將32768Hz的高頻方波信號經(jīng)32768（152）次分頻后得到1Hz的方波信號供秒計數(shù)器進行計數(shù)。分頻器實際上也就是計數(shù)器。該電路可通過CD4060與雙D觸發(fā)器74LS74共同實現(xiàn)。
（3）時間計數(shù)器電路：時間計數(shù)電路由秒個位和秒十位計數(shù)器、分個位和分十位計數(shù)器及時個位和時十位計數(shù)器電路構(gòu)成，其中秒個位和秒十位計數(shù)器、分個位和分十位計數(shù)器為60進制計數(shù)器，而根據(jù)設(shè)計要求，時個位和時十位計數(shù)器為24進制計數(shù)器。計數(shù)器可以使用十進制的74LS160。
（4）譯碼驅(qū)動電路：譯碼驅(qū)動電路將計數(shù)器輸出的8421BCD碼轉(zhuǎn)換為數(shù)碼管需要的邏輯狀態(tài)，并且為保證數(shù)碼管正常工作提供足夠的工作電流。譯碼器可以使用CD4511。
（5）校時電路：可以通過基本的門器件、電阻與開關(guān)實現(xiàn)。由設(shè)計的電路圖可選擇與非門74LS00。（6）整點報時電路：一般時鐘都應(yīng)具備整點報時電路功能,即在時間出現(xiàn)整點前數(shù)秒內(nèi),數(shù)字鐘會自動報時,以示提醒.其作用方式是發(fā)出連續(xù)的或有節(jié)奏的音頻聲波。
3、電路調(diào)試方法與結(jié)果說明（1）電路調(diào)試方法 ①數(shù)碼管的調(diào)試：可以用萬用表的負極接數(shù)碼管的3或8腳，正極依次接數(shù)碼管剩余的管腳所接電阻的另一端，并將萬用表調(diào)至測發(fā)光二極管檔位，從而測試數(shù)碼管的顯示是否正確。②“時”“分”“秒”電路的調(diào)試：將“時”“分”“秒”電路連接完成后，可以用函數(shù)信號發(fā)生器產(chǎn)生的1Hz方波信號分別作為“時”、“分”、“秒”的個位74LS160的計數(shù)脈沖，從而測試“時”是否為24進制，“分”和“秒”是否為60進制。③校時電路的調(diào)試：先將電路外接用函數(shù)信號發(fā)生器產(chǎn)生的2Hz方波信號，再分別通過校時、校分電路開關(guān)的斷開、閉合以及開關(guān)閉合后電路的工作情況判斷電路的校時、校分功能是否正確。
④秒脈沖產(chǎn)生電路的調(diào)試：將電路產(chǎn)生的秒時間脈沖接入示波器，觀察并計算電路是否產(chǎn)生1Hz方波信號。（2）結(jié)果說明
①數(shù)碼管的調(diào)試：當(dāng)正極依次接1、2、4、5、7、9、10管腳時，數(shù)碼管依次是G、F、A、B、C、D、E亮。②“時”“分”“秒”電路的調(diào)試：“時”為24進制（從“00”到“23”），“分”和“秒”都為60進制（從“00”到“59”）。
③校時電路的調(diào)試：開關(guān)斷開時電路處于正常工作狀態(tài)，開關(guān)閉合時電路處于校時、校分狀態(tài)。
④秒脈沖產(chǎn)生電路的調(diào)試：電路產(chǎn)生1Hz方波信號。
4、軟件設(shè)計說明書與流程圖（1）秒脈沖產(chǎn)生電路
晶體振蕩器是構(gòu)成數(shù)字式時鐘的核心，它保證了時鐘的走時準(zhǔn)確及穩(wěn)定。由于晶體具有較高的頻率穩(wěn)定性及準(zhǔn)確性，從而保證了輸出頻率的穩(wěn)定和準(zhǔn)確。晶體XTAL的頻率選為32768HZ。該元件專為數(shù)字鐘電路而設(shè)計，其頻率較低，有利于減少分頻器級數(shù)。從有關(guān)手冊中，可查得C1、C2均為20pF。當(dāng)要求頻率準(zhǔn)確度和穩(wěn)定度更高時，還可接入校正電容并采取溫度補償措施。由于CMOS電路的輸入阻抗極高，因此反饋電阻R1可選為22MΩ。較高的反饋電阻有利于提高振蕩頻率的穩(wěn)定性。通常，數(shù)字鐘的晶體振蕩器輸出頻率較高，為了得到1Hz的秒信號輸入，需要對振蕩器的輸出信號進行分頻。通常實現(xiàn)分頻器的電路是計數(shù)器電路，一般采用多級２進制計數(shù)器來實現(xiàn)。
本實驗中采用CD4060來構(gòu)成分頻電路。管腳圖見圖2。CD4060在數(shù)字集成電路中可實現(xiàn)的分頻次數(shù)最高，而且CD4060還包含振蕩電路所需的非門，使用更為方便。CD4060計數(shù)為14級2進制計數(shù)器，可以將32768Hz的信號分頻為2Hz，再經(jīng)過74LS74即可獲得1Hz的方波信號。原理電路圖如圖3所示，圖4為仿真電路圖。
圖2 D4060管腳圖
圖3 CD4060秒脈沖振蕩發(fā)生器
圖 4 產(chǎn)生1Hz時間脈沖的電路圖
（2）時間計數(shù)器電路 ①“秒”“分”電路
根據(jù)題目要求，“秒”和“分”都是60進制的，而且是從“00”到“59”，可以使用十進制的74LS160來實現(xiàn)這個功能。首先將兩片74LS160通過串行進位方式接成百進制計數(shù)器，即分別將“秒”和“分”個位的進位輸出信號經(jīng)非門作為“秒”和“分”十位的計數(shù)輸入脈沖。當(dāng)計數(shù)器從全0狀態(tài)開始計數(shù)，計入59個脈沖時，經(jīng)與非門譯碼產(chǎn)生低電平信號立刻將兩片74LS160同時置零，于是便得到了60進制的計數(shù)器。74160的邏輯功能示意圖、引腳圖及功能表如下所示。
圖5 a)74160邏輯功能示意圖
b)74160引腳圖
圖6 74160邏輯功能表 ②“時”電路 根據(jù)題目要求，“時”是24進制的，而且是從“00”到“23”，可以使用十進制的74LS160來實現(xiàn)這個功能。首先將兩片74LS160通過串行進位方式接成百進制計數(shù)器，當(dāng)計數(shù)器從全0狀態(tài)開始計數(shù)，計入23個脈沖時，經(jīng)與非門譯碼產(chǎn)生低電平信號立刻將兩片74LS160同時置零，于是便得到了24進制的計數(shù)器。（3）譯碼驅(qū)動電路
計數(shù)器實現(xiàn)了對時間的累計以8421BCD碼形式輸出，選用顯示譯碼電路將計數(shù)器的輸出數(shù)碼轉(zhuǎn)換為數(shù)碼顯示器件所需要的輸出邏輯和一定的電流，選用CD4511作為顯示譯碼電路，選用LED數(shù)碼管作為顯示單元電路。由于CD4511是輸出高電平有效，所以選用七段共陰極LED數(shù)碼管。若將“秒”、“分”、“時”計數(shù)器的每位輸出分別接到相應(yīng)七段譯碼器的輸入端，便可進行不同數(shù)字的顯示。“秒”用數(shù)碼管顯示如圖7所示。
圖7 “秒”的譯碼及驅(qū)動顯示電路圖（4）校時電路
數(shù)字種啟動后,每當(dāng)數(shù)字鐘顯示與實際時間不符合,需要根據(jù)標(biāo)準(zhǔn)時間進行校時。通常，校正時間的方法是：首先截斷正常的計數(shù)通路，然后再進行人工觸發(fā)計數(shù)或?qū)㈩l率較高的方波信號加到需要校正的計數(shù)單元的輸入端，校正好后，再轉(zhuǎn)入正常計時狀態(tài)即可。校“秒”時，采用等待校時。校“分”、“時”的原理比較簡單，采用加速校時。對校時電路的要求是 : 1．在小時校正時不影響分和秒的正常計數(shù)。2．在分校正時不影響秒和小時的正常計數(shù)。當(dāng)開關(guān)斷開時，因為校正信號和0相與的輸出為0，而開關(guān)的另一端接高電平，正常輸入信號可以順利通過與或門，故校時電路處于正常計時狀態(tài)；當(dāng)開關(guān)閉合時，情況正好與上述相反，這時校時電路處于校時狀態(tài)。與非門可選74LS00，非門則可用與非門2個輸入端并接來代替從而節(jié)省芯片。校時電路圖見圖8。
校時電路圖（5）整點報時電路
一般時鐘都應(yīng)具備整點報時電路功能，即在時間出現(xiàn)整點前數(shù)秒內(nèi)，數(shù)字鐘會自動報時，以示提醒。其作用方式是發(fā)出連續(xù)的或有節(jié)奏的音頻聲波。當(dāng)時間在59分50秒到59分59秒期間時，分十位、分個位和秒十位均保持不變，分別為5、9和5，因此可將分計數(shù)器十位的QC和QＡ、個位的QＤ和QＡ及秒計數(shù)器十位的QＣ 和QＡ相與。電路在整點前6秒鐘內(nèi)開始整點報時，即當(dāng)時間在59分54秒到59分59秒期間時，報時電路產(chǎn)生報時控制信號，控制小喇叭產(chǎn)生低音；當(dāng)時間為00分00秒時，報時電路產(chǎn)生報時控制信號，控制小喇叭產(chǎn)生高音。
5、軟件調(diào)試方法與運行結(jié)果說明（1）軟件調(diào)試方法
由于仿真時晶振不能正常工作，所以通過外接1KHz方波信號來調(diào)試電路。“時”“分”“秒”電路的調(diào)試：“時”為24進制（從“00”到“23”），“分”和“秒”都為60進制（從“00”到“59”）。校時電路的調(diào)試：可以通過校時、校分電路的開關(guān)來校對時間，并判斷電路的“時”“分”“秒”的進制是否正確。開關(guān)斷開時電路處于正常工作狀態(tài)，開關(guān)閉合時電路處于校時、校分狀態(tài)。（2）運行結(jié)果說明
數(shù)碼管的各部分可以正確顯示，電路的“時”為24進制（從“00”到“23”），“分”和“秒”都為60進制（從“00”到“59”）。開關(guān)斷開時電路處于正常工作狀態(tài)，開關(guān)閉合時電路處于校時、校分狀態(tài)，通過控制開關(guān)及輸入信號可以達到校時功能。
三、設(shè)計體會與建議 1.設(shè)計體會
我覺得此次的數(shù)字鐘設(shè)計實驗，電路原理相對來比較簡單，但電路圖比較復(fù)雜，所用芯片比較多，相應(yīng)的連線也多，這就給焊接電路增加了較大的難度。不過通過此次實驗，使我更進一步地熟悉了芯片的結(jié)構(gòu)，掌握了實驗中所用各芯片的工作原理和其具體的使用方法，同時還接觸到了一些新認識的芯片，增長了見識。這次課程設(shè)計是一次難得的鍛煉機會，讓我們能夠充分運用所學(xué)過的理論知識和自己動手實際操作的能力，另外還讓我們學(xué)習(xí)查找資料的方法，以及自己設(shè)計電路、焊接電路、分析解決電路存在的問題的能力。這對于我來說是很好的提高，填補了平日理論學(xué)習(xí)后實踐方面的空白。參考文獻
[1] 閻石.數(shù)字電子技術(shù)基礎(chǔ)[M].北京：高等教育出版社，2001年
[2] 楊素行.模擬電子技術(shù)基礎(chǔ)簡明教程[M].北京：高等教育出版社，2005年 [3]康華光.電子技術(shù)基礎(chǔ)[M].北京：高等教育出版社，1999年 [4]彭華林等編.數(shù)字電子技術(shù)[M].長沙：湖南大學(xué)出版社，2004年 [5]金唯香等編.電子測試技術(shù)[M].長沙：湖南大學(xué)出版社，2004年
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